1. Field of the Invention
The present invention relates to a non-volatile ferroelectric memory device having differential data, and more specifically, to a non-volatile ferroelectric memory device, in which cell arrays sharing a main bit line are divided into two groups by a sense amplifier located at the center therebetween, and differential data are stored in cells corresponding to at least two main bit lines (main bit line group) of the divided cell array groups.
2. Description of the Related Art
Generally, a ferroelectric random access memory (hereinafter, referred to as ‘FeRAM’) has a data processing speed as fast as a Dynamic Random Access Memory DRAM and conserves data even after the power is turned off.
The FeRAM having structures similar to the DRAM includes the capacitors made of a ferroelectric substance, so that it utilizes the characteristic of a high residual polarization of the ferroelectric substance in which data is not deleted even after an electric field is eliminated.
FIG. 1 is a schematic diagram of a unit memory cell of a related art 1T1C embedded non-volatile ferroelectric memory device.
In the unit memory cell shown in FIG. 1, a bit line BL is formed in one direction and a word line WL is formed in a transverse direction with respect to the bit line BL. A plate line PL is formed in the same direction as the word line WL, being at a predetermined distance therefrom. An NMOS transistor TR has a gate connected to the word line WL and a source connected to the bit line BL. A ferroelectric capacitor FC has a first electrode connected to a drain of the NMOS transistor and a second electrode is connected to the plate line PL.
FIG. 2 is a timing diagram illustrating an operation of the memory cell in FIG. 1.
When a word line WL and a plate line PL in a selected cell are activated, a charge corresponding to a data “1” or “0” stored in the ferroelectric capacitor FC is applied to the bit line BL. In other words, voltages having different levels are generated in the bit line BL depending on the cell data.
FIG. 3 is a schematic diagram of a cell array block and a sensing amplifier in a related art non-volatile ferroelectric memory device having a hierarchical bit line architecture.
The cell array blocks BLK0–BLKn are vertically positioned symmetrical with respect to common data buses BUS(0)–BUS(n). Each main bit line MBL of the cell array block BLK 0–BLK n is selectively coupled to data bus BUS(0)–BUS(n) by a column selection unit C/S. Each cell array block BLK0–BLKn has a hierarchical bit line architecture including a plurality of sub bit lines (not shown) selectively coupled to one of the main bit lines MBL. In the hierarchical structure, a voltage applied to the sub bit line (not shown) is converted into current for inducing voltage change in the main bit line MBL. A sensing voltage induced on the main bit line is transferred to a sense amplifier S/A through the data buses BUS(0)–BUS(n). The sense amplifier S/A compares the sensing voltage transferred through the data buses BUS(0)–BUS(n) with a pre-determined reference voltage V_REF, and senses a cell data. Here, the common data buses BUS(0)–BUS(n) are shared by the cell array blocks BLK 0–BLK n, and each bus line of the data buses BUS(0)–BUS(n) is coupled to a main bit line MBL in each cell array block BLK 0–BLK n.
FIG. 4 is a circuit diagram illustrating in detail the cell array having a hierarchical bit line architecture and the column selection unit C/S shown in FIG. 3.
The sub bit lines SBL is connected a plurality of memory cells having a 1T1C (1 Transistor 1 Capacitor) structure which are connected between word lines WL(0)–WL(m−1) and plate lines PL(0)–PL(m−1). When an NMOS transistor T3 is turned on after a sub bit line selection signal SBSW1 is activated, a load on the main bit line MBL is reduced to one sub bit line SBL level. In addition, when an NMOS transistor T4 is turned on after a sub bit line pull-down signal SBPD is activated, the sub bit line SBL is adjusted to the ground voltage level.
A sub bit line pull-up signal SBPU is a signal for adjusting power supply to the sub bit line SBL, and a sub bit line selection signal SBSW2 adjusts a signal for applying the sub bit line pull-up signal SBPU to the sub bit line SBL.
The main bit line MBL is selectively coupled to the common data bus BUS(0) by a column selection unit C/S that turns on/off in response to a column selection signal CS0.
The sense amplifier S/A compares the sensing voltage transferred through the data buses BUS(0)–BUS(n) with the pre-determined reference voltage V_REF, and senses a cell data. Then the sense amplifier S/A outputs SA_OUT to a data buffer (not shown).
FIG. 5 is a timing diagram for explaining the operation of the circuit illustrated in FIG. 4.
When a word line WL and a plate line PL are activated to a high level, the voltage levels on the sub bit line SBL and the main bit line MBL are determined depending on a data value of a corresponding memory cell. For example, if the data value in a cell is high, the voltage level on the sub bit line SBL is increased and thus, the amount of current flowing through the NMOS transistor T6 becomes larger. As a result, the voltage level of the main bit line MBL is reduced to a great degree. On the contrary, if the data value in the cell is low, the voltage on the sub bit line SBL is lowered and thus, the amount of current flowing through the NMOS transistor T6 becomes smaller. In this case, however, the voltage level of the main bit line MBL is reduced only slightly.
As described above, the level of a sensing voltage induced on the main bit line MBL is changed depending on the cell data (i.e. the data value), and when the column selection signal CS0 is activated, the sensing voltage is transferred to the sense amplifier S/A through a common data bus. The sense amplifier S/A compares the sensing voltage on the main bit line MBL with the reference voltage V_REF, and senses a cell data.
However, in the above-described system where the reference voltage is compared with the sensing voltage induced by a unit cell in order to sense a data in the corresponding cell, noise caused by an external impact is often generated in the reference voltage and as a result of this, a precise data sensing is not obtained. In addition, in the case of the related art 1T1C embedded memory cell where a 1-bit data is stored in one single unit cell and is sensed, if the ferroelectric capacitor of a selected cell is in abnormal state (WEAK), the sensing voltage is reduced and thus, sensing a data in a corresponding cell cannot be done as accurately as possible. Unfortunately this problem gets worse when the driving voltage of a chip becomes lower.
Moreover, because the sensing voltage induced on the main bit line is transferred to a sense amplifier through a common data bus, the common data bus acts as another factor of data sensing delay.